Low Power Decoding Circuits for Ultra Portable Devices

A wide spread of existing and emerging battery driven wireless devices do not necessarily demand high data rates. Rather, ultra low power, portability and low cost are the most desired characteristics. Examples of such applications are wireless sensor networks (WSN), body area networks (BAN), and a variety of medical implants and health-care aids. Being small, cheap and low power for the individual transceiver nodes, let those to be used in abundance in remote places, where access for maintenance or recharging the battery is limited. In such scenarios, the lifetime of the battery, in most cases, determines the lifetime of the individual nodes. Therefore, energy consumption has to be so low that the nodes remain operational for an extended period of time, even up to a few years. It is known that using error correcting codes (ECC) in a wireless link can potentially help to reduce the transmit power considerably. However, the power consumption of the coding-decoding hardware itself is critical in an ultra low power transceiver node. Power and silicon area overhead of coding-decoding circuitry needs to be kept at a minimum in the total energy and cost budget of the transceiver node. In this thesis, low power approaches in decoding circuits in the framework of the mentioned applications and use cases are investigated. The presented work is based on the 65nm CMOS technology and is structured in four parts as follows: In the first part, goals and objectives, background theory and fundamentals of the presented work is introduced. Also, the ECC block in coordination with its surrounding environment, a low power receiver chain, is presented. Designing and implementing an ultra low power and low cost wireless transceiver node introduces challenges that requires special considerations at various levels of abstraction. Similarly, a competitive solution often occurs after a conclusive design space exploration. The proposed decoder circuits in the following parts are designed to be embedded in the low power receiver chain, that is introduced in the first part. Second part, explores analog decoding method and its capabilities to be embedded in a compact and low power transceiver node. Analog decod- ing method has been theoretically introduced over a decade ago that followed with early proof of concept circuits that promised it to be a feasible low power solution. Still, with the increased popularity of low power sensor networks, it has not been clear how an analog decoding approach performs in terms of power, silicon area, data rate and integrity of calculations in recent technologies and for low data rates. Ultra low power budget, small size requirement and more relaxed demands on data rates suggests a decoding circuit with limited complexity. Therefore, the four-state (7,5) codes are considered for hardware implementation. Simulations to chose the critical design factors are presented. Consequently, to evaluate critical specifications of the decoding circuit, three versions of analog decoding circuit with different transistor dimensions fabricated. The measurements results reveal different trade-off possibilities as well as the potentials and limitations of the analog decoding approach for the target applications. Measurements seem to be crucial, since the available computer-aided design (CAD) tools provide limited assistance and precision, given the amount of calculations and parameters that has to be included in the simulations. The largest analog decoding core (AD1) takes 0.104mm2 on silicon and the other two (AD2 and AD3) take 0.035mm2 and 0.015mm2, respectively. Consequently, coding gain in trade-off with silicon area and throughput is presented. The analog decoders operate with 0.8V supply. The achieved coding gain is 2.3 dB at bit error rates (BER)=0.001 and 10 pico-Joules per bit (pJ/b) energy efficiency is reached at 2 Mbps. Third part of this thesis, proposes an alternative low power digital decoding approach for the same codes. The desired compact and low power goal has been pursued by designing an equivalent digital decoding circuit that is fabricated in 65nm CMOS technology and operates in low voltage (near-threshold) region. The architecture of the design is optimized in system and circuit levels to propose a competitive digital alternative. Similarly, critical specifications of the decoder in terms of power, area, data rate (speed) and integrity are reported according to the measurements. The digital implementation with 0.11mm2 area, consumes minimum energy at 0.32V supply which gives 9 pJ/b energy efficiency at 125 kb/s and 2.9 dB coding gain at BER=0.001. The forth and last part, compares the proposed design alternatives based on the fabricated chips and the results attained from the measurements to conclude the most suitable solution for the considered target applications. Advantages and disadvantages of both approaches are discussed. Possible extensions of this work is introduced as future work

Low power analog channel decoder in sub-threshold 65nm CMOS

This paper presents the architecture and the corresponding simulation results for a very low power half-rate extended Hamming (8,4) decoder implemented in analog integrated circuitry. TI’s 65nm low power CMOS design library was used to simulate the complete decoder including an input interface, an analog decoding core and an output interface. The simulated bit error rate (BER) performance of the decoder is presented and compared to the ideal performance expected from the Hamming code. Transistor-level simulation results suggest that a high throughput Hamming decoder up to 1 Mbits can be implemented in analog circuits with a core power consumption as low as 6 μW

An Analog (7,5) Convolutional Decoder in 65 nm CMOS for Low Power Wireless Applications

A complete architecture with transistor level simulation is presented for a low power analog convolutional decoder in 65 nm CMOS. The decoder core operates in the weak inversion (sub-VT) and realizes the BCJR decoding algorithm corresponding to the 4-state tail-biting trellis of a (7,5) convolutional code. The complete decoder also incorporates serial I/O digital interfaces and current mode differential DACs. The simulated bit error rate is presented to illustrate the coding gain compared to an uncoded system. Our results show that a low power, high throughput convolutional decoder up to 1.25 Mb/s can be implemented using analog circuitry with a total power consumption of 84 μW. For low rate applications the decoder consumes only 47 μW at a throughput of 250 kb/s

Transistor sizing for a 4-state current mode analog channel decoder in 65-nm CMOS

Analog decoders are constructed based on interconnecting CMOS Gilbert vector multipliers using transistors operating in the sub-VT region. They are seen as an interesting alternative to digital implementations with a low transistor count and a potential for a very low power consumption. Analog implementation makes the circuit sensitive to mismatch, requiring careful transistor sizing. A simulation technique combining Monte-Carlo analysis in Spectre with Matlab processing has therefore been used to investigate transistor sizing for an analog (7,5) convolutional decoder. The simulation results indicate that with a tail-biting trellis circle size 14 with transistor size W/L = 1.0μm/0.6μm, the decoder can offer close to maximum coding gain while operating on very low currents when implemented in 65-nm CMOS technology

A 3μW 500 kb/s ultra low power analog decoder with digital I/O in 65 nm CMOS

Measurement results of an analog channel decoder in 65 nm CMOS are presented. We target ultra compact and low power applications with low to medium throughput requirements. The decoding core is designed for (7,5)(8) convolutional codes and takes 0.104 mm(2) on silicon. The degrading effects of analog imperfections are investigated and the presented results allow power, performance and throughput trade-offs. Analyzing the bit error rate (BER) performance under extreme power constraints provides insights on energy efficiency and limitations of small scale analog decoders. For the limited power budget of 3 W the decoder performs the required computations to provide 1 dB of coding gain at BER=0.001 for 500 kb/s throughput. The presented chip has digital I/O that facilitates embedding it in a conventional digital receiver